1. Field of the Invention
The present invention relates generally to computer aided methods and tools for designing, simulating, and verifying integrated circuit (IC) designs. More specifically, the present invention relates to a process of generating a synoptic layout database allowing for efficient layout parasitic extraction and circuit simulation in post-layout verification of an IC design.
2. Description of the Prior Art
The design of an ultra large scale integrated (ULSI) circuit, or a very large scale integrated (VLSI) circuit is a very time-consuming process, even with the use of computer aided design (CAD) systems. VLSI CAD systems support descriptions of hardware at various levels of abstraction, such as system, sub-system, register, gate, circuit, and layout levels. Such systems allow designers to design a hardware device at an abstract level and progressively work down to the layout level.
Most VLSI CAD systems support a layout editor (e.g., the Virtuoso IC Layout and Verification System available from Cadence Design Systems, Inc. of San Jose, Calif.) for generating a layout database which provides a geometric representation of an IC design. A layout database may be represented in a standard format such as the Cal-Tech Intermediate format (CIF), or the GDS2 standard format. A layout database typically includes geometric parameters associated with geometric objects, or geometries (e.g., polygons), specifying the position and dimension of different layers of materials to be laid on a silicon wafer. The geometries are typically converted into respective rectangles arranged according to their physical location and commonly represented by parameter values in the form of coordinates.
The layout an IC design may be described in terms of a symbolic layout, or logical layout, rather than in terms of the actual geometry of the masks and layers that comprise the chip. A symbolic layout provides a higher level of abstraction than a mask layout, and is therefore easier to manipulate. In a symbolic layout, primitive components of an IC design may be organized in groups referred to as "cells", and the layout may be described in terms of the cells and their relative placement and interconnection. A cell that contains only primitive symbols (i.e. transistors, wires, capacitors and other physical components) is referred to as a "leaf cell".
There are a variety of symbolic layout methodologies commonly used by layout designers for logically representing an IC layout. Modern layout editors typically allow designers to select from multiple symbolic layout methodologies in order to accommodate different performance objectives. For example, in a hierarchical representation, a symbolic layout is treated as a hierarchical structure with multiple levels. Each level is a symbolic layout of various cells and primitive components. Another commonly used symbolic layout methodology involves creating a boundary layer which is a logical layer of a layout database wherein each cell is defined by a cell boundary which may be defined by the IC designer using a layout editor. Also, a designer may attribute cell names to each type of cell used in the design.
Layout editors also provide tools for minimizing the overall area of a layout (i.e., the size of the chip). Typical layout tools allow a designer to create individual layout cells including polygons, each layout cell representing a corresponding circuit structure (e.g., a NAND gate, a multiplier, a memory unit). The layout cells may be stored in files called cell libraries for use by the designer.
VLSI CAD systems also support verification, synthesis, and testing of IC designs. Post-Layout IC verification processes include layout parasitic extraction (LPE), design rule checking (DRC), and connectivity analysis. Design rules insure that an IC layout design is functional and capable of manufacture (e.g., design rules may prohibit a circuit layout from being designed with short circuits). IC analysis is also performed to verify that the electrical interconnections of a semiconductor chip correspond to an originally intended design once it has been determined that the design rules have been followed correctly (i.e., connectivity analysis). IC analysis for DRC and/or connectivity analysis is performed by examining the layout geometry of an IC. During examination of the layout, an actual net list may be generated which represents the interconnections of all elements on the chip.
FIG. 1 shows a block diagram at 10 illustrating a prior art system for layout parasitic extraction and circuit stimulation in post layout verification. The system 10 includes: a layout extraction program 12 for receiving an input layout database 14 generated by a layout editor (not shown), and for generating a circuit net list 16; and a circuit simulator 18 for receiving the net list 16, and for generating performance characteristics 20 of the IC design. The layout extraction program 12 traces the layout of an IC design represented by the input layout database 14, and constructs the net list 16 which is a net list of an actual layout. The actual net list extracted from a layout database may be compared with a desired net list representative of the desired electrical connectivity. This comparison may be done by a layout versus schematic (LVS) program (not shown). If the actual net list does not agree with the desired net list, it is likely that an error exists in the computer software for constructing the layout.
Layout extraction refers to a process of converting a layout data base into an electric circuit representation including transistors, resistors, capacitors. etc. The extracted electric circuit may then be used for simulation. For large scale IC designs, the layout extraction process is computationally intensive, and therefore time consuming. Compaction methods, which include compressing geometric data of a layout database, are examples of prior art methods for reducing the time required for layout extraction. However, even with the use of compaction methods, the layout extraction process remains computationally intensive, and time consuming.
As circuit designs continue to increase in size, the traditional process for layout extraction and circuit simulation in post-layout verification become impractical due to the time required in extracting these circuit designs from layout database. A layout database for a ULSI or VLSI circuit design may include millions of geometric objects.
What is needed is a more efficient layout parasitic extraction process which is less computationally intensive and therefore less time consuming.
What is also needed is more efficient circuit simulation process in post layout verification.